Thermal Modeling of Si?N? Photonic Integrated Circuits for Low-Power Data Interconnects

As artificial intelligence and data-driven computing continue to expand exponentially, data centers are projected to consume nearly 10% of global electricity within the next decade. This rapid increase in energy demand has motivated the search for new computing hardware that can reduce thermal losses and improve power efficiency. Photonic integrated circuits (PICs) represent one of the most promising alternatives to traditional electronic interconnects. By using light instead of electrical signals, PICs enable high-bandwidth, low-latency data transmission while minimizing resistive heating and power inefficiencies. In particular, silicon nitride (Si₃N₄) PICs are being investigated for long-range interconnects due to their ultra-low propagation loss.

In this study, we use computational modeling to evaluate heat transport in thermally actuated Si₃N₄ photonic devices. The simulations reveal how device geometry and fabrication parameters influence heat confinement and tuning efficiency, providing design insights relevant to large-scale photonic systems. We present an undercut thermal isolation method, computationally predicted to improve power efficiency by up to 26×, that is readily implementable through isotropic reactive ion etching (RIE) in real devices. Improved thermal management in Si₃N₄ PICs can enable more densely integrated, power-efficient photonic systems capable of supporting the increasing computational workload of modern data infrastructure.

Overall, this study presents a computational approach to thermal management and fabrication process design for energy-efficient photonic hardware in data and AI infrastructure. More broadly, this approach can also inform process optimization in traditional microelectronic and microelectromechanical systems.