(169e) All Copper Flip-Chip Packaging

A novel fabrication technique using electroless copper deposition has been used to produce all-copper chip-to-substrate connections. Industry standard flip-chip connections use solder balls at the first level of packaging to make electrical connections between the integrated circuit and its substrate. Solder has many weaknesses in flip-chip applications and faces ever greater problems as the size and pitch of the solder balls shrink with device scaling. The International Technology Roadmap for Semiconductors forecasts minimum pitch for area-array connections to shrink to 130 µm, 100 µm, and 90 µm, in 2010, 2015, and 2020, respectively. The small stand-off height accompanying fine-pitch solder balls exacerbates the problems associated with underfill materials in small gaps, which are needed with solder. Solder forms brittle copper-tin intermetallics during reflow that can compromise its thermo-mechanical reliability. Solder also has low electromigration resistance which is becoming more important as the diameter of the flip-chip connections shrink and DC power requirements increase.

All-copper connections from chip-to-substrate eliminate many of the issues with solder, underfill, and the intermetallics formed between tin and copper. Copper has superior electrical conductivity and electromigration resistance versus solder. In fact, the allowable current density for electroless deposited copper is typically 10^3 greater compared to typical solder connections. It also has superior mechanical properties compared to solder, such as yield stress and Young's modulus. These mechanical values, along with the ability to fabricate high aspect ratio connections, can be used to form mechanically compliant interconnect structures. The elimination of underfill will improve the electrical environment of the signal I/O by lowering the permittivity and loss, as well as simplify the process flow. The flip-chip signal environment will become increasingly important with time as the off-chip frequency continues to rise1. Having no tin-based materials in the I/O pathway eliminates brittle intermetallics and would improve the thermo-mechanical reliability of the metallurgical joint. Finally, high aspect ratio, fine-pitch copper connections can be fabricated without compromising the minimum stand-off distances between the chip and substrate. The elimination of solder, under-bump metallurgy needed for solder, flux, underfill, and stripping chemicals could reduce costs and harmful environmental impact.

This process replaces solder by electrolessly joining copper pillars on the chip and substrate. Solid copper-to-copper bonding was demonstrated using electroless copper followed by low-temperature annealing at 180oC for 1 hour in a nitrogen environment. Process feasibility has been demonstrated. In this talk, the mechanics of the copper pillar and fabrication process will be discussed. Pillars need to have high aspect ratio so that coefficient of thermal expansion mismatch between the chip and substrate does not cause component fracture. Polymer supporting collars around the base of the copper pillars are an effective way to distribute the stress over wider areas so as to lower the highest stress points. In this talk, the mechanicals of the pillar deformation will be presented through mechanical testing and modeling.