(428d) Optimization of New Ultralow-K Materials for Vlsi Multilevel Interconnection

The demand for increased signal transmission speed and device density for the next generation of multilevel integrated circuits has placed stringent demands on materials performance. Currently, integration of the ultra low-k materials in dual Damascene requires chemical mechanical polishing (CMP) to planarize the copper. Unfortunately, none of the commercially proposed dielectric candidates display the desired mechanical and thermal properties for successful CMP. A new polydiacetylene thermosetting polymer (PTEB-DEB) which displays a low dielectric constant (low-k) of 2.7 was recently developed. This novel material appears to offer the only avenue for designing an ultra low k dielectric (1.85k), which can still display the desired modulus (7.7Gpa) and hardness (2.0Gpa) sufficient to withstand the process of CMP.

In this talk, we will present recent additional studies to further characterize the thermal properties of spin-on PDEB-TEB ultra-thin film. These include the coefficient of thermal expansion(CTE), biaxial thermal stress, and thermal conductivity. Thus the CTE in the perpendicular direction is 2.0*10-5K-1 and in planar direction 8.0*10-6K-1. The low CTE provides a better match to the Si substrate which also to minimize interfacial stress and greatly enhance the reliability of the microprocessors. Initial experiments with oxygen plasma etching suggest a high probability of success for achieving vertical profiles.